Embodiments of the present invention relate to clock signal generators, and more particularly to a differentially synchronized output clock signal produced by complementary or single ended pattern generation logic.
A clock signal generator is commonly employed in a variety of applications, including communications and timing circuitry. Typically, a seed frequency is used to generate one or more clock signals. Desirable clock signal generators should have good noise suppression, low power consumption, and small fabrication area characteristics.
Referring to FIG. 1, a block diagram of a pattern generator 100 in accordance with the conventional art is shown. The pattern generator 100 comprises a seed frequency generator 110, a differential-to-single ended converter 120, and pattern generation logic 130. The seed frequency generator 110 typically provides a differential seed frequency signal 140. The differential seed frequency signal 140 is then converted to a single ended seed frequency signal 150 by the differential-to-single ended converter 120. The pattern generation logic 130 receives the single ended seed frequency signal 150 and generates one or more single ended pattern signals 160 based thereupon. Hence, the circuit realizes a method of providing a single ended pattern signal 160 from a differential seed frequency signal 140.
The single ended pattern generation logic 130 typically triggers on an edge of the seed frequency signal. The triggering event occurs when the falling and/or rising edge passes a threshold value. In physical implementations the threshold value moves in accordance with noise present on the power supply. A practical single ended seed frequency signal 150 also has a finite rise and fall time. Thus, when a single ended seed frequency signal 150 having a finite rise and/or fall time passes through a threshold point which is moving in accordance with noise present on the power supply, the trigger events are shifted in time, which results in jitter on the single ended pattern signal 160. Thus, even if a single ended signal has a perfect waveform shape, jitter is created. Similarly, if the threshold value does not move, but the single ended seed frequency signal 150 has a noisy waveform shape, jitter is also created.
Jitter may also result from trace-coupled noise, and the like. A single ended pattern signal 160 originating from the differential seed frequency generator 110 also suffers from noise coupling in the differential-to-single ended converter 120. Single ended signal 150, 160 paths are also susceptible to noise coupling. In addition, single ended signals 150, 160 crossing power supply boundaries incur jitter due to shifting signal levels and threshold values. Hence, the single ended pattern signal 160 is disadvantageous in that the single ended pattern signal 160 is sensitive to noise.
Referring now to FIG. 2, a block diagram of another pattern generator 200 in accordance with the conventional art is shown. The pattern generator 200 comprises a seed frequency generator 210 and pattern generation logic 220. The seed frequency generator 210 provides a differential seed frequency signal 230. The pattern generation logic 220 receives the differential seed frequency signal 230 and generates a differential pattern signal 240 based thereupon. Hence, the circuit realizes a method of providing a differential pattern signal 240 from a differential seed frequency signal 230.
Differential signals effectively carry their own reference signal. The inherent reference signal is utilized to reject common mode noise and thus reduce the deviation of triggering events from their intended periodic occurrence in time. Therefore, the differential pattern generation logic 220 significantly reduces the amount of jitter generated from system noise. The differential pattern signal 240 path also allows for common mode rejection of noise coupled on the differential pattern signal 240 path. However, this method is disadvantageous in that differential circuits requires more power and occupy a larger fabrication area than single ended circuits. They are also more complex to design and build thereby increasing cost.
Referring now to FIG. 3, another pattern generator 300 in accordance with the conventional art is shown. The pattern generator 300 comprises a seed frequency generator 310, a differential-to-single ended converter 320, pattern:generation logic 330, a transmission gate 370 and an inverter 375. The seed frequency generator 310 provides a differential seed frequency signal 340. The differential seed frequency signal 340 is then converted to a single ended seed frequency signal 350 by the differential-to-single ended converter 320. The pattern generation logic 330 receives the single ended seed frequency signal 350 and generates a single ended pattern signal 360 based thereupon. A complimentary, pseudo differential, pattern signal 380 is then generated by passing the single ended pattern signal 360 through the inverter 375. The transmission gate 370 is utilized to match the propagation delay introduced by the inverter 375. Hence, the circuit realizes a method of providing a complimentary pattern signal 380 from a differential seed frequency signal 340.
The complimentary, pseudo differential, circuit requires less power and occupies a smaller area. The complimentary signal also provides the ability to reject common mode noise coupled on the complimentary pattern signal 380 path. However, this method is disadvantageous in that the complimentary, pseudo differential, pattern signal 380 is difficult to control and typically is not exactly 180xc2x0 out of phase and therefore suffers from noise induced jitter. In addition, the jitter from the pattern generation logic is not removed, because the pattern generation logic is single ended.
Embodiments of the present invention provide a novel pattern generator, including circuitry for generating a sampled differential pattern signal. In one embodiment of the present invention, a differential seed frequency signal is converted to a single ended seed frequency signal. The single ended seed frequency signal is then used to generate a single ended pattern signal. A sampled differential pattern signal is then generated by sampling the single ended pattern signal according to the differential seed frequency signal.
In another embodiment of the present invention, a differential seed frequency signal is utilized to sample a complimentary pattern signal and convert it to a sampled differential pattern signal. By generating the sampled differential pattern signal in this fashion, a differential clock signal having reduced jitter is generated, while the clock pattern can be generated with single ended logic.
In another embodiment of the present invention, a first output of a voltage controlled oscillator generates a single ended seed frequency signal, which is fed to a divider circuit. The divider circuit generates a first complimentary signal, which is fed to the data input of a differential flip-flop circuit. A second output of the voltage controlled oscillator generates a differential seed frequency signal, which is fed to the sample clock of the differential flip-flop. The output of the differential flip-flop is then supplied to a buffer circuit.
By sampling the first complimentary signal using the differential seed frequency signal, data jitter is substantially eliminated in a resulting sampled differential signal. Therefore, any Boolean function performed on clock signals in order to generated the output clock signal can be done using single ended logic and then converted to fully differential form for better noise suppression. The seed frequency generator supplies a fully differential trigger timing event to the differential sampler. Thus, the same timing performance is achieved as if the entire circuit was differential.
Embodiments of the present invention are advantageous in that a sampled differential pattern signal path is less sensitive to supply and trace coupled noise and the like. Embodiments of the present invention are also advantageous in that the sampled differential pattern signal exhibits reduced jitter compared to single ended and complimentary, pseudo differential, clock signal generation methods. Embodiments of the present invention are also advantageous in that conversion of single ended signals to sampled differential signals allows the seed frequency signal and output clock signal to be entirely differential, while utilizing single ended pattern generation logic for lower power and less area. Embodiments of the present invention are also advantageous in that multiple patterns can be sampled from the same seed frequency generator. Embodiments of the present invention are also advantageous in that circuits generating multiple patterns can have a common supply without suffering from noise coupling.